A retiming-based test pattern generator design for built-in self test of data path architectures
نویسندگان
چکیده
Recently, a new Built-In Self Test (BIST) methodology based on balanced bistable sequential kernels has been proposed that reduces the area overhead and performance degradation associated with the conventional BILBO-oriented BIST methodology. This new methodology guarantees high fault coverage but requires special test sequences and test pattern generator (TPG) designs. In this paper, we demonstrate the use of the retiming technique in designing TPGs for balanced bistable sequential kernels. Experimental results on ISCAS benchmark circuits demonstrate the effectiveness of the designed TPGs in achieving higher fault coverage than the conventional maximal-length LFSR TPGs.
منابع مشابه
Low Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-Test
Problem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This normally requires more number of test patterns for testin...
متن کاملImproving the Timing of Extended Finite State Machines Via Catalyst
We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical path often forms a cycle and thus cannot be cut down easily by popular techniques such as pipelining or retiming. The proposed technique, based on the concept of catalyst, adds a functionally redundant block – which i...
متن کاملPerformance of Generic and Recursive Pseudo Exhaustive Two-Pattern Generator
The main objective of this research is to design a Built-in self-test (BIST) technique based on pseudo-exhaustive testing. Two pattern test generator is used to provide high fault coverage. To provides fault coverage of detectable combinational faults with minimum number of test patterns than the conventional exhaustive test pattern generation, increases the speed of BIST and may posses minimum...
متن کاملHybrid Cellular Automata-Based Pseudo Random Sequence Generator for BIST Implementation
The technique of Test pattern generation plays a key role in Built-In-Self-Test(BIST) architecture implementation. Main problem with any test pattern generator is to produce extended, random path succession which is applied to Circuit Under Test(CUT) for detecting faults. As real long numbers can be acquired as a part of physical developments only, these are complex to be employed inactual appl...
متن کاملLow Transition Test Pattern Generator Architecture for Mixed Mode Built-in-self-test (bist)
In Built-In Self-Test (BIST), test patterns are generated and applied to the circuit-under-test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers (LFSR). Conventional LFSRs normally requires more number of test patterns for test...
متن کامل